6502 ASM
6502 Processor Instruction Set
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6502 Registers & Status Flags
A (Accumulator)
8-bit primary register
X (Index X)
8-bit index register
Y (Index Y)
8-bit index register
SP (Stack Pointer)
8-bit ($0100-$01FF)
PC (Program Counter)
16-bit address
P (Status Register)
NV-BDIZC flags
Status Register (P) Flags
| Bit | Flag | Name | Description |
|---|---|---|---|
| 7 | N | Negative | Set if result bit 7 is set |
| 6 | V | Overflow | Set on signed overflow |
| 5 | - | Unused | Always 1 |
| 4 | B | Break | Set when BRK executed |
| 3 | D | Decimal | Binary/Decimal mode |
| 2 | I | Interrupt | IRQ disable |
| 1 | Z | Zero | Set if result is zero |
| 0 | C | Carry | Carry/Borrow flag |
Addressing Modes
| Mode | Format | Example | Bytes | Description |
|---|---|---|---|---|
| Immediate | #nn | LDA #$FF | 2 | Use value nn |
| Zero Page | nn | LDA $44 | 2 | Address $00nn |
| Zero Page,X | nn,X | LDA $44,X | 2 | Address $00nn+X |
| Zero Page,Y | nn,Y | LDX $44,Y | 2 | Address $00nn+Y |
| Absolute | nnnn | LDA $C000 | 3 | Address $nnnn |
| Absolute,X | nnnn,X | LDA $C000,X | 3 | Address $nnnn+X |
| Absolute,Y | nnnn,Y | LDA $C000,Y | 3 | Address $nnnn+Y |
| Indirect | (nnnn) | JMP ($FFFC) | 3 | Address at $nnnn |
| Indexed Indirect | (nn,X) | LDA ($44,X) | 2 | Address at $00nn+X |
| Indirect Indexed | (nn),Y | LDA ($44),Y | 2 | Address at $00nn, then +Y |
| Implied | - | INX | 1 | No operand |
| Accumulator | A | ROL A | 1 | Operate on A |
| Relative | nn | BEQ $06 | 2 | PC + signed nn |
Load/Store Operations
| Mnemonic | Operation | Flags | Modes | Cycles |
|---|---|---|---|---|
| LDA | Load Accumulator (A = M) | N Z | imm, zp, zpx, abs, abx, aby, idx, idy | 2-6 |
| LDX | Load X Register (X = M) | N Z | imm, zp, zpy, abs, aby | 2-4 |
| LDY | Load Y Register (Y = M) | N Z | imm, zp, zpx, abs, abx | 2-4 |
| STA | Store Accumulator (M = A) | - | zp, zpx, abs, abx, aby, idx, idy | 3-6 |
| STX | Store X Register (M = X) | - | zp, zpy, abs | 3-4 |
| STY | Store Y Register (M = Y) | - | zp, zpx, abs | 3-4 |
Register Transfers
| Mnemonic | Operation | Flags | Cycles |
|---|---|---|---|
| TAX | Transfer A to X (X = A) | N Z | 2 |
| TAY | Transfer A to Y (Y = A) | N Z | 2 |
| TXA | Transfer X to A (A = X) | N Z | 2 |
| TYA | Transfer Y to A (A = Y) | N Z | 2 |
| TSX | Transfer SP to X (X = SP) | N Z | 2 |
| TXS | Transfer X to SP (SP = X) | - | 2 |
Stack Operations
| Mnemonic | Operation | Flags | Cycles | Notes |
|---|---|---|---|---|
| PHA | Push A on Stack | - | 3 | SP-- |
| PHP | Push P on Stack | - | 3 | SP-- |
| PLA | Pull A from Stack | N Z | 4 | SP++ |
| PLP | Pull P from Stack | All | 4 | SP++ |
Stack grows downward from $01FF to $0100
Arithmetic Operations
| Mnemonic | Operation | Flags | Modes | Cycles |
|---|---|---|---|---|
| ADC | Add with Carry (A = A + M + C) | N V Z C | imm, zp, zpx, abs, abx, aby, idx, idy | 2-6 |
| SBC | Subtract with Carry (A = A - M - !C) | N V Z C | imm, zp, zpx, abs, abx, aby, idx, idy | 2-6 |
Always set carry before subtraction (SEC) and clear before addition (CLC) unless using carry intentionally
Logical Operations
| Mnemonic | Operation | Flags | Modes | Cycles |
|---|---|---|---|---|
| AND | Logical AND (A = A & M) | N Z | imm, zp, zpx, abs, abx, aby, idx, idy | 2-6 |
| ORA | Logical OR (A = A | M) | N Z | imm, zp, zpx, abs, abx, aby, idx, idy | 2-6 |
| EOR | Exclusive OR (A = A ^ M) | N Z | imm, zp, zpx, abs, abx, aby, idx, idy | 2-6 |
Shifts & Rotates
| Mnemonic | Operation | Flags | Modes | Cycles |
|---|---|---|---|---|
| ASL | Arithmetic Shift Left (C ← [76543210] ← 0) | N Z C | acc, zp, zpx, abs, abx | 2-7 |
| LSR | Logical Shift Right (0 → [76543210] → C) | N Z C | acc, zp, zpx, abs, abx | 2-7 |
| ROL | Rotate Left (C ← [76543210] ← C) | N Z C | acc, zp, zpx, abs, abx | 2-7 |
| ROR | Rotate Right (C → [76543210] → C) | N Z C | acc, zp, zpx, abs, abx | 2-7 |
Increments & Decrements
| Mnemonic | Operation | Flags | Modes | Cycles |
|---|---|---|---|---|
| INC | Increment Memory (M = M + 1) | N Z | zp, zpx, abs, abx | 5-7 |
| INX | Increment X (X = X + 1) | N Z | impl | 2 |
| INY | Increment Y (Y = Y + 1) | N Z | impl | 2 |
| DEC | Decrement Memory (M = M - 1) | N Z | zp, zpx, abs, abx | 5-7 |
| DEX | Decrement X (X = X - 1) | N Z | impl | 2 |
| DEY | Decrement Y (Y = Y - 1) | N Z | impl | 2 |
Branch Instructions
| Mnemonic | Operation | Condition | Cycles |
|---|---|---|---|
| BCC | Branch if Carry Clear | C = 0 | 2-4 |
| BCS | Branch if Carry Set | C = 1 | 2-4 |
| BEQ | Branch if Equal (Zero) | Z = 1 | 2-4 |
| BNE | Branch if Not Equal | Z = 0 | 2-4 |
| BMI | Branch if Minus (Negative) | N = 1 | 2-4 |
| BPL | Branch if Plus (Positive) | N = 0 | 2-4 |
| BVC | Branch if Overflow Clear | V = 0 | 2-4 |
| BVS | Branch if Overflow Set | V = 1 | 2-4 |
Branches take 2 cycles if not taken, 3 if taken, 4 if page boundary crossed
Jumps & Calls
| Mnemonic | Operation | Flags | Modes | Cycles |
|---|---|---|---|---|
| JMP | Jump to Address | - | abs, ind | 3-5 |
| JSR | Jump to Subroutine | - | abs | 6 |
| RTS | Return from Subroutine | - | impl | 6 |
| RTI | Return from Interrupt | All | impl | 6 |
Status Flag Operations
| Mnemonic | Operation | Flag Effect | Cycles |
|---|---|---|---|
| CLC | Clear Carry | C = 0 | 2 |
| CLD | Clear Decimal | D = 0 | 2 |
| CLI | Clear Interrupt Disable | I = 0 | 2 |
| CLV | Clear Overflow | V = 0 | 2 |
| SEC | Set Carry | C = 1 | 2 |
| SED | Set Decimal | D = 1 | 2 |
| SEI | Set Interrupt Disable | I = 1 | 2 |
Compare Instructions
| Mnemonic | Operation | Flags | Modes | Cycles |
|---|---|---|---|---|
| CMP | Compare A with Memory | N Z C | imm, zp, zpx, abs, abx, aby, idx, idy | 2-6 |
| CPX | Compare X with Memory | N Z C | imm, zp, abs | 2-4 |
| CPY | Compare Y with Memory | N Z C | imm, zp, abs | 2-4 |
Compare sets flags as if subtraction occurred: C=1 if register ≥ memory
Bit Test
| Mnemonic | Operation | Flags | Modes | Cycles |
|---|---|---|---|---|
| BIT | Bit Test A with Memory | N V Z | zp, abs | 3-4 |
BIT sets N to bit 7, V to bit 6, and Z if (A & M) = 0
System Functions
| Mnemonic | Operation | Flags | Cycles | Notes |
|---|---|---|---|---|
| BRK | Force Break (Software Interrupt) | B I | 7 | Pushes PC+2, P; jumps to IRQ vector |
| NOP | No Operation | - | 2 | Do nothing for 2 cycles |
Common Illegal/Undocumented Opcodes
| Mnemonic | Operation | Hex Codes | Description |
|---|---|---|---|
| LAX | LDA + LDX | $A7, $B7, $AF, $BF, $A3, $B3 | Load A and X simultaneously |
| SAX | Store A & X | $87, $97, $8F, $83 | Store (A AND X) to memory |
| DCP | DEC + CMP | $C7, $D7, $CF, $DF, $DB, $C3, $D3 | Decrement then compare |
| ISB | INC + SBC | $E7, $F7, $EF, $FF, $FB, $E3, $F3 | Increment then subtract |
| SLO | ASL + ORA | $07, $17, $0F, $1F, $1B, $03, $13 | Shift left then OR |
| RLA | ROL + AND | $27, $37, $2F, $3F, $3B, $23, $33 | Rotate left then AND |
⚠️ Illegal opcodes are not guaranteed to work on all 6502 variants!
Opcode Quick Reference
By Hex Value (Official Opcodes)
x0 x1 x2 x3 x4 x5 x6 x7 x8 x9 xA xB xC xD xE xF
0x BRK ORA --- --- --- ORA ASL --- PHP ORA ASL --- --- ORA ASL ---
1x BPL ORA --- --- --- ORA ASL --- CLC ORA --- --- --- ORA ASL ---
2x JSR AND --- --- BIT AND ROL --- PLP AND ROL --- BIT AND ROL ---
3x BMI AND --- --- --- AND ROL --- SEC AND --- --- --- AND ROL ---
4x RTI EOR --- --- --- EOR LSR --- PHA EOR LSR --- JMP EOR LSR ---
5x BVC EOR --- --- --- EOR LSR --- CLI EOR --- --- --- EOR LSR ---
6x RTS ADC --- --- --- ADC ROR --- PLA ADC ROR --- JMP ADC ROR ---
7x BVS ADC --- --- --- ADC ROR --- SEI ADC --- --- --- ADC ROR ---
8x --- STA --- --- STY STA STX --- DEY --- TXA --- STY STA STX ---
9x BCC STA --- --- STY STA STX --- TYA STA TXS --- --- STA --- ---
Ax LDY LDA LDX --- LDY LDA LDX --- TAY LDA TAX --- LDY LDA LDX ---
Bx BCS LDA --- --- LDY LDA LDX --- CLV LDA TSX --- LDY LDA LDX ---
Cx CPY CMP --- --- CPY CMP DEC --- INY CMP DEX --- CPY CMP DEC ---
Dx BNE CMP --- --- --- CMP DEC --- CLD CMP --- --- --- CMP DEC ---
Ex CPX SBC --- --- CPX SBC INC --- INX SBC NOP --- CPX SBC INC ---
Fx BEQ SBC --- --- --- SBC INC --- SED SBC --- --- --- SBC INC ---
Cycle Counts by Addressing Mode
| Instruction | Imm | ZP | ZP,X/Y | Abs | Abs,X/Y | (Ind,X) | (Ind),Y |
|---|---|---|---|---|---|---|---|
| LDA/LDX/LDY | 2 | 3 | 4 | 4 | 4+ | 6 | 5+ |
| STA/STX/STY | - | 3 | 4 | 4 | 5 | 6 | 6 |
| ADC/SBC | 2 | 3 | 4 | 4 | 4+ | 6 | 5+ |
| AND/ORA/EOR | 2 | 3 | 4 | 4 | 4+ | 6 | 5+ |
| CMP/CPX/CPY | 2 | 3 | 4 | 4 | 4+ | 6 | 5+ |
| INC/DEC | - | 5 | 6 | 6 | 7 | - | - |
| ASL/LSR/ROL/ROR | 2* | 5 | 6 | 6 | 7 | - | - |
+ = Add 1 cycle if page boundary crossed
* = Accumulator mode
* = Accumulator mode
Interrupt Vectors
| Vector | Address | Triggered By |
|---|---|---|
| NMI | $FFFA-$FFFB | Non-Maskable Interrupt |
| RESET | $FFFC-$FFFD | System Reset |
| IRQ/BRK | $FFFE-$FFFF | Interrupt Request / BRK |
Programming Tips
Zero Page Optimization: Use zero page for frequently accessed variables - saves 1 byte and 1+ cycles per access
Branch vs Jump: Use branches for short jumps (±127 bytes) - saves 1 byte and cycles
Loop Counters: Count down to zero when possible - DEX/DEY automatically set Z flag
16-bit Operations: Store low byte first (little-endian) for 16-bit values
Fast Clear: LDA #0 / STA addr is faster than INC/DEC to zero
Multiply by 2: ASL is faster than ADC with itself
Test for Zero/Negative: Most instructions set N and Z flags - no need for explicit CMP #0
Reference Note: This cheat sheet covers the NMOS 6502. The 65C02 (CMOS) adds additional instructions and addressing modes. The 65816 extends to 16-bit with many more features.