z80 ASM

Z80 Processor Instruction Set

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Z80 Registers & Flags

Main Register Set

A (Accumulator)

8-bit primary register

F (Flags)

Status flags register

B, C

8-bit general purpose
BC = 16-bit pair

D, E

8-bit general purpose
DE = 16-bit pair

H, L

8-bit general purpose
HL = 16-bit pair (memory pointer)

Alternate Register Set

A', F'

Alternate accumulator & flags

B', C'

Alternate BC pair

D', E'

Alternate DE pair

H', L'

Alternate HL pair

Special Registers

IX

16-bit index register X

IY

16-bit index register Y

SP

16-bit stack pointer

PC

16-bit program counter

I

Interrupt vector register

R

Memory refresh register

Flag Register (F)

BitFlagNameDescription
7SSignSet if result is negative (bit 7 = 1)
6ZZeroSet if result is zero
5YCopy of bit 5Undocumented, copy of bit 5 of result
4HHalf CarryCarry from bit 3 to bit 4
3XCopy of bit 3Undocumented, copy of bit 3 of result
2P/VParity/OverflowParity or Overflow depending on operation
1NAdd/SubtractSet for subtract operations
0CCarryCarry from bit 7

Addressing Modes

ModeFormatExampleDescription
ImmediatenLD A,55H8-bit immediate data
Immediate ExtendednnLD HL,1234H16-bit immediate data
RegisterrLD A,BRegister addressing
Register Indirect(rr)LD A,(HL)Memory pointed by register pair
Indexed(IX+d), (IY+d)LD A,(IX+5)Index register + signed displacement
Extended(nn)LD A,(5000H)Direct memory address
RelativeeJR 10HPC + signed displacement
Bit AddressingbSET 3,ABit position 0-7
I/O Port(n), (C)IN A,(20H)8-bit port address or BC register

Register Notation

r, r': Any 8-bit register (A, B, C, D, E, H, L)
dd: Register pair BC, DE, HL, SP
qq: Register pair BC, DE, HL, AF
pp: Register pair BC, DE, IX, SP (with DD prefix)
rr: Register pair BC, DE, IY, SP (with FD prefix)

8-Bit Load Group

MnemonicOperationFlagsOpcodesCycles
LD r,r'r ← r'-40-7F (except 76)4
LD r,nr ← n-06,0E,16,1E,26,2E,3E7
LD r,(HL)r ← (HL)-46,4E,56,5E,66,6E,7E7
LD r,(IX+d)r ← (IX+d)-DD 46,4E,56,5E,66,6E,7E19
LD r,(IY+d)r ← (IY+d)-FD 46,4E,56,5E,66,6E,7E19
LD (HL),r(HL) ← r-70-77 (except 76)7
LD (IX+d),r(IX+d) ← r-DD 70-7719
LD (IY+d),r(IY+d) ← r-FD 70-7719
LD (HL),n(HL) ← n-3610
LD (IX+d),n(IX+d) ← n-DD 3619
LD (IY+d),n(IY+d) ← n-FD 3619
LD A,(BC)A ← (BC)-0A7
LD A,(DE)A ← (DE)-1A7
LD A,(nn)A ← (nn)-3A13
LD (BC),A(BC) ← A-027
LD (DE),A(DE) ← A-127
LD (nn),A(nn) ← A-3213
LD A,IA ← IS Z H=0 P/V N=0ED 579
LD A,RA ← RS Z H=0 P/V N=0ED 5F9
LD I,AI ← A-ED 479
LD R,AR ← A-ED 4F9

16-Bit Load Group

MnemonicOperationFlagsOpcodesCycles
LD dd,nndd ← nn-01,11,21,3110
LD IX,nnIX ← nn-DD 2114
LD IY,nnIY ← nn-FD 2114
LD HL,(nn)H ← (nn+1), L ← (nn)-2A16
LD dd,(nn)dd ← (nn)-ED 4B,5B,6B,7B20
LD IX,(nn)IX ← (nn)-DD 2A20
LD IY,(nn)IY ← (nn)-FD 2A20
LD (nn),HL(nn+1) ← H, (nn) ← L-2216
LD (nn),dd(nn) ← dd-ED 43,53,63,7320
LD (nn),IX(nn) ← IX-DD 2220
LD (nn),IY(nn) ← IY-FD 2220
LD SP,HLSP ← HL-F96
LD SP,IXSP ← IX-DD F910
LD SP,IYSP ← IY-FD F910
PUSH qq(SP-1) ← qqH, (SP-2) ← qqL, SP ← SP-2-C5,D5,E5,F511
PUSH IXPush IX onto stack-DD E515
PUSH IYPush IY onto stack-FD E515
POP qqqqL ← (SP), qqH ← (SP+1), SP ← SP+2-C1,D1,E1,F110
POP IXPop IX from stack-DD E114
POP IYPop IY from stack-FD E114

Exchange, Block Transfer, and Search

MnemonicOperationFlagsOpcodesCycles
EX DE,HLDE ↔ HL-EB4
EX AF,AF'AF ↔ AF'-084
EXXBC ↔ BC', DE ↔ DE', HL ↔ HL'-D94
EX (SP),HLH ↔ (SP+1), L ↔ (SP)-E319
EX (SP),IXIX ↔ (SP)-DD E323
EX (SP),IYIY ↔ (SP)-FD E323
LDI(DE) ← (HL), DE++, HL++, BC--H=0 P/V N=0ED A016
LDIRRepeat LDI until BC=0H=0 P/V=0 N=0ED B021/16
LDD(DE) ← (HL), DE--, HL--, BC--H=0 P/V N=0ED A816
LDDRRepeat LDD until BC=0H=0 P/V=0 N=0ED B821/16
CPICompare A with (HL), HL++, BC--S Z H P/V N=1ED A116
CPIRRepeat CPI until A=(HL) or BC=0S Z H P/V N=1ED B121/16
CPDCompare A with (HL), HL--, BC--S Z H P/V N=1ED A916
CPDRRepeat CPD until A=(HL) or BC=0S Z H P/V N=1ED B921/16
Block instructions: P/V is set if BC≠0 after operation

8-Bit Arithmetic Group

MnemonicOperationFlagsOpcodesCycles
ADD A,rA ← A + rS Z H P/V N=0 C80-874
ADD A,nA ← A + nS Z H P/V N=0 CC67
ADD A,(HL)A ← A + (HL)S Z H P/V N=0 C867
ADD A,(IX+d)A ← A + (IX+d)S Z H P/V N=0 CDD 8619
ADC A,sA ← A + s + CYS Z H P/V N=0 C88-8F, CE4-19
SUB sA ← A - sS Z H P/V N=1 C90-97, D64-19
SBC A,sA ← A - s - CYS Z H P/V N=1 C98-9F, DE4-19
AND sA ← A ∧ sS Z H=1 P/V N=0 C=0A0-A7, E64-19
OR sA ← A ∨ sS Z H=0 P/V N=0 C=0B0-B7, F64-19
XOR sA ← A ⊕ sS Z H=0 P/V N=0 C=0A8-AF, EE4-19
CP sA - s (compare)S Z H P/V N=1 CB8-BF, FE4-19
INC rr ← r + 1S Z H P/V N=004,0C,14,1C,24,2C,3C4
INC (HL)(HL) ← (HL) + 1S Z H P/V N=03411
INC (IX+d)(IX+d) ← (IX+d) + 1S Z H P/V N=0DD 3423
DEC rr ← r - 1S Z H P/V N=105,0D,15,1D,25,2D,3D4
DEC (HL)(HL) ← (HL) - 1S Z H P/V N=13511
DEC (IX+d)(IX+d) ← (IX+d) - 1S Z H P/V N=1DD 3523

16-Bit Arithmetic Group

MnemonicOperationFlagsOpcodesCycles
ADD HL,ssHL ← HL + ssH N=0 C09,19,29,3911
ADC HL,ssHL ← HL + ss + CYS Z H P/V N=0 CED 4A,5A,6A,7A15
SBC HL,ssHL ← HL - ss - CYS Z H P/V N=1 CED 42,52,62,7215
ADD IX,ppIX ← IX + ppH N=0 CDD 09,19,29,3915
ADD IY,rrIY ← IY + rrH N=0 CFD 09,19,29,3915
INC ssss ← ss + 1-03,13,23,336
INC IXIX ← IX + 1-DD 2310
INC IYIY ← IY + 1-FD 2310
DEC ssss ← ss - 1-0B,1B,2B,3B6
DEC IXIX ← IX - 1-DD 2B10
DEC IYIY ← IY - 1-FD 2B10

General-Purpose Arithmetic and CPU Control

MnemonicOperationFlagsOpcodesCycles
DAADecimal Adjust AccumulatorS Z H P/V C274
CPLA ← Ā (complement)H=1 N=12F4
NEGA ← 0 - AS Z H P/V N=1 CED 448
CCFCY ← C̄YH N=0 C3F4
SCFCY ← 1H=0 N=0 C=1374
NOPNo operation-004
HALTHalt CPU-764
DIIFF1,IFF2 ← 0-F34
EIIFF1,IFF2 ← 1-FB4
IM 0Set interrupt mode 0-ED 468
IM 1Set interrupt mode 1-ED 568
IM 2Set interrupt mode 2-ED 5E8

Rotate and Shift Group

MnemonicOperationFlagsOpcodesCycles
RLCARotate A left circularH=0 N=0 C074
RLARotate A left through carryH=0 N=0 C174
RRCARotate A right circularH=0 N=0 C0F4
RRARotate A right through carryH=0 N=0 C1F4
RLC rRotate r left circularS Z H=0 P/V N=0 CCB 00-078
RLC (HL)Rotate (HL) left circularS Z H=0 P/V N=0 CCB 0615
RLC (IX+d)Rotate (IX+d) left circularS Z H=0 P/V N=0 CDD CB d 0623
RL mRotate m left through carryS Z H=0 P/V N=0 CCB 10-178-23
RRC mRotate m right circularS Z H=0 P/V N=0 CCB 08-0F8-23
RR mRotate m right through carryS Z H=0 P/V N=0 CCB 18-1F8-23
SLA mShift m left arithmeticS Z H=0 P/V N=0 CCB 20-278-23
SRA mShift m right arithmeticS Z H=0 P/V N=0 CCB 28-2F8-23
SRL mShift m right logicalS Z H=0 P/V N=0 CCB 38-3F8-23
RLDRotate left digit (A,HL)S Z H=0 P/V N=0ED 6F18
RRDRotate right digit (A,HL)S Z H=0 P/V N=0ED 6718

Bit Set, Reset, and Test Group

MnemonicOperationFlagsOpcodesCycles
BIT b,rTest bit b of rZ H=1 N=0CB 40-7F8
BIT b,(HL)Test bit b of (HL)Z H=1 N=0CB 46-7E12
BIT b,(IX+d)Test bit b of (IX+d)Z H=1 N=0DD CB d 46-7E20
SET b,rSet bit b of r-CB C0-FF8
SET b,(HL)Set bit b of (HL)-CB C6-FE15
SET b,(IX+d)Set bit b of (IX+d)-DD CB d C6-FE23
RES b,rReset bit b of r-CB 80-BF8
RES b,(HL)Reset bit b of (HL)-CB 86-BE15
RES b,(IX+d)Reset bit b of (IX+d)-DD CB d 86-BE23

Jump Group

MnemonicOperationFlagsOpcodesCycles
JP nnPC ← nn-C310
JP cc,nnIf cc true, PC ← nn-C2,CA,D2,DA,E2,EA,F2,FA10
JR ePC ← PC + e-1812
JR C,eIf C=1, PC ← PC + e-3812/7
JR NC,eIf C=0, PC ← PC + e-3012/7
JR Z,eIf Z=1, PC ← PC + e-2812/7
JR NZ,eIf Z=0, PC ← PC + e-2012/7
JP (HL)PC ← HL-E94
JP (IX)PC ← IX-DD E98
JP (IY)PC ← IY-FD E98
DJNZ eB--, if B≠0 then PC ← PC + e-1013/8

Condition Codes

NZ
Z = 0
Z
Z = 1
NC
C = 0
C
C = 1
PO
P/V = 0
PE
P/V = 1
P
S = 0
M
S = 1

Call and Return Group

MnemonicOperationFlagsOpcodesCycles
CALL nn(SP-1) ← PCH, (SP-2) ← PCL, PC ← nn-CD17
CALL cc,nnIf cc true, CALL nn-C4,CC,D4,DC,E4,EC,F4,FC17/10
RETPCL ← (SP), PCH ← (SP+1)-C910
RET ccIf cc true, RET-C0,C8,D0,D8,E0,E8,F0,F811/5
RETIReturn from interrupt-ED 4D14
RETNReturn from NMI-ED 4514
RST pCALL to address p-C7,CF,D7,DF,E7,EF,F7,FF11
RST addresses: 00H, 08H, 10H, 18H, 20H, 28H, 30H, 38H

Input and Output Group

MnemonicOperationFlagsOpcodesCycles
IN A,(n)A ← (n)-DB11
IN r,(C)r ← (C)S Z H=0 P/V N=0ED 40,48,50,58,60,68,7812
INI(HL) ← (C), B--, HL++Z N=1ED A216
INIRRepeat INI until B=0Z=1 N=1ED B221/16
IND(HL) ← (C), B--, HL--Z N=1ED AA16
INDRRepeat IND until B=0Z=1 N=1ED BA21/16
OUT (n),A(n) ← A-D311
OUT (C),r(C) ← r-ED 41,49,51,59,61,69,7912
OUTI(C) ← (HL), B--, HL++Z N=1ED A316
OTIRRepeat OUTI until B=0Z=1 N=1ED B321/16
OUTD(C) ← (HL), B--, HL--Z N=1ED AB16
OTDRRepeat OUTD until B=0Z=1 N=1ED BB21/16

Instruction Prefixes

PrefixHexPurposeExample
CBCBBit operations prefixCB 46 = BIT 0,(HL)
DDDDIX register operationsDD 21 = LD IX,nn
EDEDExtended instructionsED 44 = NEG
FDFDIY register operationsFD 21 = LD IY,nn
DD CBDD CBIX bit operationsDD CB 05 46 = BIT 0,(IX+5)
FD CBFD CBIY bit operationsFD CB 05 46 = BIT 0,(IY+5)

Instruction Timing

Z80 instruction timing is measured in T-states (clock cycles). The timings shown are for standard Z80 at 4MHz. Actual execution time = T-states × (1/clock_frequency)

Timing Notes

  • Conditional instructions show two timings: taken/not taken
  • Block instructions (LDIR, CPIR, etc.) show timings for BC≠0/BC=0
  • Memory access adds wait states on some systems
  • Interrupt acknowledgment adds 2 T-states minimum
  • M1 cycle (opcode fetch) typically takes 4 T-states

Undocumented Instructions

⚠️ These instructions work on NMOS Z80 but may not work on all variants (CMOS, clones)
MnemonicOperationDescription
SLL mShift left logical, set bit 0Like SLA but sets bit 0
IXH, IXLAccess IX high/low bytesUse IX as two 8-bit registers
IYH, IYLAccess IY high/low bytesUse IY as two 8-bit registers
IN (C)Input to flags onlySets flags but discards data
OUT (C),0Output zeroOutputs 0 to port C

Undocumented Flags

  • Bit 3 (X flag) and Bit 5 (Y flag) usually copy bits 3 and 5 of the result
  • Used by some programs for copy protection or optimization
  • DAA instruction behavior depends on these undocumented flags

Programming Tips

Register Pairs: Use HL for memory pointers, BC for counters, DE for data transfer
Shadow Registers: Use EX AF,AF' and EXX for fast context switching in interrupt handlers
Block Instructions: LDIR/LDDR are powerful but slow - unroll for speed-critical code
Index Registers: IX/IY instructions are 4 bytes and slow - use HL when possible
Conditional Jumps: JR is 1 byte shorter than JP for short jumps (±126 bytes)
Stack Operations: PUSH/POP preserve register pairs efficiently
I/O Operations: Use OTIR/INIR for fast block I/O transfers
Interrupt Modes: IM 2 provides vectored interrupts for complex systems

Z80 vs 8080 Differences

FeatureZ808080
RegistersAF, BC, DE, HL + alternates, IX, IY, I, RAF, BC, DE, HL only
Instructions158 official + extensions78 instructions
AddressingIndexed, bit addressing, block operationsBasic modes only
InterruptsNMI, 3 interrupt modesSingle interrupt
PowerSingle +5V supplyMultiple voltages
ClockSingle-phase clockTwo-phase clock
Reference Note: This cheat sheet covers the standard NMOS Z80. The CMOS versions (Z80C, Z84C00) have lower power consumption and some timing differences. Modern variants like the eZ80 extend to 24-bit addressing.